The present invention relates to nitride semiconductor devices and method for fabricating the nitride semiconductor devices, and particularly relates to a power transistor for use in, for example, a power supply circuit and a method for fabricating the power transistor.
In recent years, field effect transistors (FETs) made of gallium nitride (GaN)-based semiconductors have been intensively studied as high-frequency high-power devices. III-V nitride semiconductors such as GaN form various types of mixed crystal together with aluminum nitride (AlN) and indium nitride (InN). Thus, GaN-based semiconductors form heterojunctions in the same manner as conventionally-used arsenic-based semiconductors such as gallium arsenide (GaAs).
In particular, a heterojunction of a nitride semiconductor has a characteristic in which spontaneous polarization and/or piezoelectric polarization produces a high concentration of carriers at the interface thereof even when the nitride semiconductor is not doped. As a result, FETs using nitride semiconductors are likely to exhibit depletion-mode (normally-on) characteristics, and thus it is difficult to obtain enhancement-mode (normally-off) characteristics. However, most of the devices currently used in the power electronics market are normally-off devices, and normally-off operation is also strongly demanded for FETs using GaN-based semiconductors.
Normally-off FETs are implemented with, for example, a structure in which a gate region is recessed so that the threshold voltage is positively shifted (see, for example, T. Kawasaki et al., “Solid State Devices and Materials 2005 tech. digest”, 2005, p. 206). A method with which a FET is fabricated on the (10-12) plane of a sapphire substrate so that no polarization electric field is generated in the crystal growth direction of nitride semiconductor (see, for example, M. Kuroda et al., “Solid State Devices and Materials 2005 tech. digest”, 2005, p. 470) is also known. In addition, as a promising structure for obtaining a normally-off FET, a junction field effect transistor (JFET) in which a p-type GaN layer is formed as gate is proposed (see, for example, Japanese Laid-Open Patent Publication No. 2005-244072). In a JFET structure, piezoelectric polarization produced at the heterointerface between a channel layer of undoped GaN and a bather layer of AlGaN is canceled by piezoelectric polarization produced at the heterointerface between the barrier layer of AlGaN and a p-type GaN layer. This structure reduces the concentration of two-dimensional electron gas immediately under a gate region where the p-type GaN layer is formed, thus obtaining normally-off characteristics. The use of a pn junction having a larger built-in potential than that of a Schottky junction for gate advantageously reduces gate leakage current even with an application of a positive gate voltage.